Signed in as:
filler@godaddy.com
Our experience in digital logic standard cells development
1. Schematic and layout designs of CMOS..
Schematic and layout designs of high quality CMOS standard cells such as:
Inverters, buffers, NAND, NOR, AND, OR, AND-OR, OR-AND, XNOR, XOR, clock gaters, delay buffers, full adder, half adder, D-Latch, D Flip Flops, Scan-D Flip Flops, Multi-bit Flip Flops, endcap cells, fillers, de-coupling fillers, tap cell, tie cells.
2. Layout verifications..
Layout verifications such as DRC, LVS, post layout extraction, and all other needed verifications tailored per technology.
3. Familiarity with foundries..
Familiarity with many different foundries such as: TSMC, UMC, GF, SMIC and Samsung.
4. Familiarity to technologies..
Familiarity to many different technologies starting from 180nm to 7nm including FinFET and FDSOI technologies.
5. Cells’ designs..
Cells’ designs based on different PPA goals with multiple VT’s and Channel Lengths.
6. Clock and POK..
Clock and POK (Power Optimization Kit) cells’ designs.
7. Familiarity to Unix..
Familiarity to Unix Operating System commands.
